Mailing List:
cores@opencores.org
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0
replies
FPU comparison
started 2008-12-17 03:28:29 UTC
2008-12-17 03:28:29 UTC
Klemen Dovrtel
9
replies
I2C controller core
started 2008-12-10 22:03:47 UTC
2008-12-16 15:04:08 UTC
Ing. Alexander Alexeis Suárez León
5
replies
OCIDEC-3.
started 2008-12-11 19:01:03 UTC
2008-12-16 05:46:14 UTC
Mark McDougall
4
replies
wishbone_bfm example
started 2008-12-07 16:56:06 UTC
2008-12-15 13:15:21 UTC
Richard Herveille
2
replies
VHDL 16550 UART core - strange tx signal
started 2008-12-14 18:02:54 UTC
2008-12-15 12:51:05 UTC
Klemen Dovrtel
8
replies
Off-the-shelf personal computer?
started 2008-12-03 15:19:39 UTC
2008-12-09 19:11:17 UTC
Jeremy Bennett
3
replies
wishbone state machine example
started 2008-12-04 14:27:59 UTC
2008-12-05 03:38:35 UTC
andrew mulcock
0
replies
raggedstone - can't meet timing constraints?
started 2008-12-05 00:55:07 UTC
2008-12-05 00:55:07 UTC
Andrew Kohlsmith (lists)
4
replies
oc8501
started 2008-12-04 07:44:52 UTC
2008-12-04 17:14:33 UTC
Thilo Jeremias
0
replies
actel fpga igloo/nano & proasic3
started 2008-12-04 10:25:29 UTC
2008-12-04 10:25:29 UTC
thilo
14
replies
Open Source creation of FPGA data files?
started 2008-07-07 00:05:15 UTC
2008-11-29 21:52:30 UTC
Mike D
1
reply
Interested in helping out
started 2008-11-27 16:13:15 UTC
2008-11-28 05:20:21 UTC
Mark McDougall
0
replies
ARINC 429 Core
started 2008-11-27 22:39:46 UTC
2008-11-27 22:39:46 UTC
s***@gmail.com
0
replies
Some questions from an FPGA newbie
started 2008-11-22 04:06:54 UTC
2008-11-22 04:06:54 UTC
b***@yahoo.com
2
replies
Some questions from an FPGA newbie
started 2008-11-11 23:08:28 UTC
2008-11-12 02:06:11 UTC
Fabrizio Fazzino
0
replies
problems with UART 16550 core
started 2008-11-11 21:01:33 UTC
2008-11-11 21:01:33 UTC
o***@ingeteam.com
1
reply
implementing or1200 on ml310 board
started 2008-11-11 16:35:42 UTC
2008-11-11 19:52:11 UTC
Jeremy Bennett
0
replies
problems with UART 16550 core
started 2008-11-06 14:33:37 UTC
2008-11-06 14:33:37 UTC
v***@intecs.it
2
replies
Request for VHDL Source Code for function interaction using DE1 Board
started 2008-11-01 18:35:28 UTC
2008-11-05 09:54:23 UTC
J***@j.com
1
reply
VHCG (Viterbi HDL Generator)
started 2008-10-30 22:21:22 UTC
2008-11-01 23:37:38 UTC
m***@gmail.com
1
reply
I2C Slave
started 2008-10-30 14:25:52 UTC
2008-10-30 22:44:16 UTC
Lee Studley
1
reply
I2c-ocore linux driver
started 2008-10-29 15:22:09 UTC
2008-10-29 21:35:53 UTC
Peter Korsgaard
0
replies
DDS
started 2008-10-24 17:20:15 UTC
2008-10-24 17:20:15 UTC
s***@opencores.org
2
replies
Verilog and vhdl use in altera schematic editor
started 2008-10-22 11:04:04 UTC
2008-10-23 06:56:38 UTC
章智慧
0
replies
PTC
started 2008-10-15 11:11:53 UTC
2008-10-15 11:11:53 UTC
karthik venkatesh
0
replies
CAN Protocol Controller : Whisbone I/F: SOLVED
started 2008-10-10 13:00:48 UTC
2008-10-10 13:00:48 UTC
p***@gmail.com
0
replies
Combo wireless core?
started 2008-10-05 20:06:10 UTC
2008-10-05 20:06:10 UTC
w***@yahoo.com.cn
4
replies
a VHDL 16550 UART core & Wishbone LPC Host and Peripheral Bridge
started 2008-09-30 17:19:32 UTC
2008-10-02 22:12:18 UTC
Matt Ettus
0
replies
$100,000 design competition is now open for entries
started 2008-10-02 00:48:51 UTC
2008-10-02 00:48:51 UTC
Fabrizio Fazzino
0
replies
a VHDL 16550 UART core & Wishbone LPC Host and
started 2008-10-01 20:34:15 UTC
2008-10-01 20:34:15 UTC
H***@OpenCores.org
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