verilog UART 16550 BFM simulation problem

[v***@rediffmail.com]

Hi Everyone,
I am testing the verilog UART 16550 core and I have written a
simple bfm test code. While monitoring the UART TX signal no change in
the signal is observed. Also while reading the LSR register at after
reset state and after writing into the fifo no change only 0x00 is coming.

We found that all the registers are updating at the reset state but
not changing through below code.

please go through this and reply as early as possible ur comments.

regards
sathish valluri

please see the simulation wave forms and bfm code below

http://docs.google.com/Doc?id=dfxv5nrb_190fprrmcgk

http://docs.google.com/Doc?id=dfxv5nrb_192ft62n9c9

wb_init( bus_c); -- initalise wishbone bus
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0005"; -- LSR
bkd_test_array(0) := X"0000_0030";
bkr_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );
report to_hex(bkd_test_array(0));

bka_test_array(0) := X"0000_0003"; -- LCR
bkd_test_array(0) := X"0000_0083"; -- 8 data bits, 1 start bit, set LCR(7)
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0001"; -- DLM
bkd_test_array(0) := X"0000_0000"; -- BAUD
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- DLL
bkd_test_array(0) := X"0000_0005"; -- BAUD
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0005"; -- LSR
bkd_test_array(0) := X"0000_0000";
bkr_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );
report to_hex(bkd_test_array(0));

bka_test_array(0) := X"0000_0003"; -- LCR
bkd_test_array(0) := X"0000_0003"; -- 8 data bits, 1 start bit, clear
LCR(7)
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0037"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

--bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
--bkd_test_array(0) := X"0000_0005"; -- data
--bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
--clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0003"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0005"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );


bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0033"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

bka_test_array(0) := X"0000_0000"; -- Transmiter fifo
bkd_test_array(0) := X"0000_0055"; -- data
bkw_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );

clock_wait( 50000, bus_c );

bka_test_array(0) := X"0000_0005"; -- LSR
bkd_test_array(0) := X"0000_0000";
bkr_32( bka_test_array, bkd_test_array, 1, bus_c);
clock_wait( 2, bus_c );
report to_hex(bkd_test_array(0));