Mailing List:
cores@opencores.org
Add newDisplay options
0
replies
Mr. gchoc-cores 80% Off on all products
started 2010-02-22 07:43:40 UTC
2010-02-22 07:43:40 UTC
Pfizer Genuine VIAGRA
0
replies
Hi, gchoc-cores, unbelievable 80% off prices
started 2010-02-22 07:34:58 UTC
2010-02-22 07:34:58 UTC
Swiss Watch on-line
1
reply
A Question
started 2009-02-26 05:20:24 UTC
2009-03-08 10:15:59 UTC
David Cary
1
reply
A Question
started 2009-03-06 18:17:18 UTC
2009-03-08 01:45:46 UTC
Morteza Shokri
2
replies
Peripherals On Demand
started 2009-02-24 21:42:43 UTC
2009-03-03 13:57:15 UTC
Fabien Marteau
0
replies
OpenCores-related internships?
started 2009-02-28 15:41:46 UTC
2009-02-28 15:41:46 UTC
Wojciech A. Koszek
2
replies
UART 16550 Addressing
started 2009-02-20 23:05:30 UTC
2009-02-22 05:06:20 UTC
Mark McDougall
0
replies
Cycle accurate modeling ORPSoC with Verilator
started 2009-02-20 04:44:38 UTC
2009-02-20 04:44:38 UTC
Jeremy Bennett
3
replies
Plasma/Xilinx problem
started 2009-02-11 15:19:03 UTC
2009-02-17 14:10:01 UTC
m***@gmail.com
2
replies
I2C syntax error in Synopsys
started 2009-02-16 02:34:52 UTC
2009-02-16 23:55:09 UTC
Richard Herveille
1
reply
uClinux on Plasma
started 2009-02-11 15:25:34 UTC
2009-02-12 00:44:15 UTC
d***@yahoo.com
0
replies
New version of VHCG released
started 2009-02-04 20:29:30 UTC
2009-02-04 20:29:30 UTC
j***@gmail.com
0
replies
uClinux on Plasma
started 2009-02-02 00:38:13 UTC
2009-02-02 00:38:13 UTC
Texblues
17
replies
GPL License - again
started 2009-01-25 16:08:22 UTC
2009-01-30 21:57:33 UTC
Rick Collins
1
reply
MII mac verilog module
started 2009-01-25 17:12:28 UTC
2009-01-26 02:40:30 UTC
m***@gmail.com
0
replies
T80 core - NoIce Debugger Problem
started 2009-01-23 01:46:12 UTC
2009-01-23 01:46:12 UTC
Antus Tibor
0
replies
UART16750
started 2009-01-14 21:52:14 UTC
2009-01-14 21:52:14 UTC
Sebastian Witt
2
replies
I2c-ocore linux driver debug
started 2009-01-13 16:00:10 UTC
2009-01-14 21:51:05 UTC
Peter Korsgaard
0
replies
Can bus
started 2009-01-13 01:06:38 UTC
2009-01-13 01:06:38 UTC
o***@terra.es
0
replies
opb2wb
started 2009-01-12 18:31:25 UTC
2009-01-12 18:31:25 UTC
o***@terra.es
0
replies
verilog UART 16550 BFM simulation problem
started 2009-01-08 15:03:59 UTC
2009-01-08 15:03:59 UTC
v***@rediffmail.com
0
replies
verilog UART 16550 BFM simulation problem
started 2009-01-02 17:38:42 UTC
2009-01-02 17:38:42 UTC
v***@rediffmail.com
0
replies
Help with a coregen wishbone wrapper
started 2008-12-31 02:30:23 UTC
2008-12-31 02:30:23 UTC
Newell Jensen
3
replies
Wishbone LPC Host & Peripheral - interrupts?
started 2008-12-22 07:25:31 UTC
2008-12-28 01:55:15 UTC
o***@dublintrees.com
0
replies
C to Verilog core generator
started 2008-12-27 20:43:49 UTC
2008-12-27 20:43:49 UTC
n***@gmail.com
14
replies
T80 Core x
started 2008-05-05 18:27:51 UTC
2008-12-26 17:06:36 UTC
Alessandro
0
replies
the errors of "tests.v" module?
started 2008-12-24 08:59:13 UTC
2008-12-24 08:59:13 UTC
j***@gmail.com
0
replies
VHCG is updated!
started 2008-12-23 13:22:19 UTC
2008-12-23 13:22:19 UTC
sheng zhu
1
reply
CRC32 Calculation
started 2008-12-21 17:22:25 UTC
2008-12-22 01:42:56 UTC
Umair Siddiqui
2
replies
opb2wb
started 2008-12-17 19:38:31 UTC
2008-12-21 14:56:53 UTC
o***@terra.es
Click to Load More...
Loading...