o***@terra.es
2008-12-17 13:38:31 UTC
Hello all, I've unziped the opb_wb.tar file into the pcores folder in the
Xilinx EDK and I've been able to generate the netlist using XPS. I've
tried to implement the desing into ISE but the following error appears.
ERROR: NgdBuild:604 - logical
block 'Inst_cpu_micro_blaze/opb2wb_0/opb2wb_0' with
type 'opb2wb' could not be resolved. A pin name misspelling can
cause this, a
missing edif or ngc file, or the misspelling of a type name.
Symbol 'opb2wb'
is not supported in target 'spartan3e'.
As I've added the line OPTION ARCH_SUPPORT = spartan3e
to the mpd file but same result.
The RTL schematic is correct and the opb2wb wrapper is connected to
the OPB bus signals correctly.
Any idea about this issue?.
Kindest Regards
Oscar
Xilinx EDK and I've been able to generate the netlist using XPS. I've
tried to implement the desing into ISE but the following error appears.
ERROR: NgdBuild:604 - logical
block 'Inst_cpu_micro_blaze/opb2wb_0/opb2wb_0' with
type 'opb2wb' could not be resolved. A pin name misspelling can
cause this, a
missing edif or ngc file, or the misspelling of a type name.
Symbol 'opb2wb'
is not supported in target 'spartan3e'.
As I've added the line OPTION ARCH_SUPPORT = spartan3e
to the mpd file but same result.
The RTL schematic is correct and the opb2wb wrapper is connected to
the OPB bus signals correctly.
Any idea about this issue?.
Kindest Regards
Oscar